1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices such as microcomputers, and more particularly to a semiconductor integrated circuit device having a means for preventing the microcomputers or the like from malfunctioning in response to the application of an abnormal voltage.
2. Description of the Related Art
Recently, a large number of various IC devices have become available. A one-chip microcomputer has been widely used for controlling devices. Many of the one-chip microcomputers use CMOS transistors (Complementary Metal Oxide Semiconductor transistors). Such one-chip microcomputers are expected to be used in various circumstances. For example, the one-chip microcomputers are used in circumstances in which excessively low or high voltages are applied to input/output terminals thereof. Such abnormal voltages cause a latchup inherent in CMOS transistor circuits. The latchup may destroy insulation of internal circuits or may cause the microcomputer to run away. In these cases, it becomes no longer possible to maintain the circuit operation in the normal state. With the above in mind, protection circuits are provided for input/output circuits of the integrated circuits. The protection circuits function to protect the input/output circuits from the abnormal voltages. When an abnormal voltage is supplied to an input/output terminal, the protection circuit coupled to the input/output terminal causes a charge resulting from the abnormal voltage to flow to the ground.
FIG. 1 is a circuit diagram of a related input interface circuit of an integrated circuit, such as a one-chip microcomputer. An input node nl connected to a pad 1 functioning as an external terminal is connected to drains of P-channel and N-channel protection transistors Q1 and Q2, both of which form a protection circuit. The drains of the protection transistors Q1 and Q2 are coupled, through a parasitic resistor R1, to gates of transistors Q3 and Q4, both of which form a CMOS inverter in the input interface circuit.
The gate and source of the protection transistor Q1 are connected to a high-potential power supply system V.sub.CC. The gate and the source of the protection transistor Q2 are connected to a low-voltage power supply system GND. A positive charge resulting from an abnormal voltage higher than the power supply voltage V.sub.CC flows to the high-potential power supply system V.sub.CC through the protection transistor Q1. A negative charge resulting from an abnormal voltage lower than the power supply voltage GND flows to the lower-potential power supply system GND through the protection transistor Q2. During the above operation, the parasitic resistor R1 functions to prevent the abnormal voltage from being directly applied to the gates of the input buffer transistors Q3 and Q4.
FIG. 2 is a cross-sectional view of a semiconductor integrated-circuit device that provides the circuit shown in FIG. 1. The P-channel and N-channel transistors Q1 and Q2 are formed in an upper surface portion of a p-type semiconductor substrate 2 so that these transistors are close to each other. Two p-type regions 11 and 12 are formed in an n-type well 3 forming the P-channel protection transistor Q1. Two p.sup.+ -type regions for forming a source 4 and a drain 5 are formed in the p-type regions 11 and 12, respectively. The source 4 and a gate 15 are connected to the high-potential power supply system V.sub.CC, and the drain 5 is connected to the pad 1. The p-type region 12 surrounding the drain 5 is connected to the input buffer transistors of the internal circuit. An n.sup.- -type region 6, which is called a stopper, is formed around the n-type well region 3 so that the source 4 and the drain 5 are formed in the n.sup.+ -type well region 3. The n.sup.+ -type region 6 is connected to the high-potential power supply system V.sub.CC at a plurality of points.
A source 7 and a drain 8 of the N-channel protection transistor Q2 are formed in n-type regions 13 and 14, respectively. The source 7 and a gate 16 are connected to the low-potential power supply system GND, and the drain 8 is connected to the pad 1. The n-type region 14 is connected, together with the p-type region 12 of the P-channel protection transistor Q1, to the input buffer transistors. A p.sup.+ -type region 9 functioning as a stopper is formed so that the source 7 and the drain 8 are formed in the p.sup.+ -type region 9, which are connected to the low-potential power supply system GND at a plurality of points. The p.sup.+ -type region 9 and the n.sup.+ -type region 6 that is connected to the high-potential power supply system V.sub.CC maintain the substrate potential at a predetermined potential, and apply a backward voltage to a diode junction interface which isolates the regions of the protection transistors Q1 and Q2 from each other.
It is known that a parasitic bipolar transistor is formed in an area in which the protection transistors Q1 and Q2 are formed. The n.sup.+ -type region on the side of the P-channel transistor Q1 serves as a base of a PNP parasitic transistor, which has an emitter formed by the drain of the P-channel transistor Q1, and a collector formed by the p.sup.+ -type region 9 on the side of the N-channel transistor Q2. Similarly, the p.sup.+ -type region 9 on the side of the N-channel transistor Q2 serves as a base of an NPN parasitic transistor, which has an emitter formed by the drain 8 of the N-channel transistor Q2 and a collector formed by the n.sup.+ -type region 6.
FIG. 3 is a circuit diagram of a circuit including a PNP bipolar transistor used as a voltage detection circuit. When a voltage higher than the voltage V.sub.CC is applied to the pad 1, the bipolar transistor Q5 conducts, and a voltage developed across an output resistor R2 is output via an inverter INV. The transistor Q5 conducts when the base-emitter voltage thereof becomes equal to or higher than 0.6 V, for example, and activates the inverter INV. The output resistor R2 has a resistance value equal to or larger than, for example, 40 k.OMEGA.. For example, a polysilicon sheet is used for forming the output resistor R2.
It will be noted that either the protection transistor Q1 or the protection transistor Q2 respond to an abnormal voltage applied to the pad 1 so that the internal circuit can be protected from the abnormal voltage. Hence, even if the abnormal voltage is continuously applied to the pad, a charge resulting from the abnormal voltage continuously flows in the protection transistor Q1 or Q2 unless the power supply systems are fused. As a result, the internal circuit will continuously operate normally.
However, if an excessive current passes through the LSI devices, the latchup inherent in the CMOS circuits may take place in the internal circuit or an abnormal voltage may be directly applied to the internal circuit from the substrate. Hence, the operation of the internal circuit will be affected. Particularly, the microcomputer may be caused to run away. If the microcomputer is designed to control a vehicle, it is specifically required that the latchup or other unwanted events be suppressed.
In order to avoid the influence of the latchup or other unwanted events, it is possible to provide noise eliminating circuits connected to terminals of the LSI chips or control the LSI chips by means of software. However, these methods increase the production costs as a whole.